Method and apparatus for constraint graph based layout compaction for integrated circuits

ABSTRACT

A method of compacting a circuit layout includes determining a critical path of the circuit layout, the critical path having a length not less than a length of each other path of the circuit layout. The method further includes representing the critical path to include a plurality of vertices and a plurality of edges, each one of the vertices being coupled to another of the vertices by an edge, the plurality of vertices including a flexible vertex corresponding to a flexible element of the circuit layout, the plurality of edges including a first shear edge. The method further includes representing the flexible vertex to include a first jogging edge. The method further includes determining an optimal cutest of the graph of the critical path, the cutest including at least one of the group consisting of the first jogging edge and the first shear edge.

FIELD OF THE INVENTION

The present invention relates to layout compaction for integratedcircuit design automation, and more particularly to constraintgraph-based layout compaction that compacts circuit elements in twodimensions during the design automation stage of a circuit layout withreduced computational requirements.

DESCRIPTION OF RELATED ART

Compaction is an important design automation stage in the phasedapproach to layout synthesis of integrated circuits (ICs), such as avery large scale integration (VLSI) design. The compaction operationconverts symbolic layouts generated by other layout synthesis tools intomask data or physical layouts and attempts to optimize the area of thelayout without changing the circuit or violating the design rules. Inother words, it is desired to make each chip as small as possible whilemaintaining design rule correctness (DRC). Today, the most attractiveapproach to mask layout compaction is graph-based compaction, whichprovides a robust basis for a one- and two-dimensional compaction.

Layout compaction algorithms typically range between one-dimensional andtwo-dimensional compaction. In one-dimensional compaction, only onecoordinate of the layout geometry is changed at a time, such as either Xcompaction or Y compaction. The goal of one-dimensional compaction is tominimize the length of one dimension or direction, whereas the otherdirection, referred to as the shear or orthogonal direction, is notaffected and remains constant. It is noted that dimension and directionare often used interchangeably herein. The goal of two-dimensionalcompaction is to modify both X and Y coordinates simultaneously in orderto minimize area. Many one-dimensional compaction algorithm versions canbe solved efficiently without consuming significant computationalresources. A few proposed versions of one-dimensional compaction andmost two-dimensional compaction proposals are “NP-hard”, which meansthat they are computationally prohibitive and not practicable. Thedifficulty of two-dimensional compaction lies in determining how the twodimensions of the layout interact to minimize the area. To circumventthe intrinsic complexity of this problem, some heuristic methods havebeen proposed to relate both dimensions of the compaction. Suchheuristic proposals are often referred to as “1.5-dimensional”compaction since, although they interrelate the two dimensions, they donot optimally solve the two-dimensional compaction problem.

Some 1.5 dimensional compaction methods have been proposed in which thelayout is essentially compacted in a preferred direction, while changingthe shear or orthogonal direction. In the process of achieving theprimary goal of decreasing the extent of the layout in the preferreddirection, these compaction techniques also make coordinate changes inthe shear direction. Each local change is called a reorganization. Oneheuristic framework has been proposed, called “super compaction”, forcarrying out feasible reorganization such that the length of the longestpath in the layout graph for the preferred direction is decreased. Thisapproach is known as “shearing” compaction. Another method to minimizethe critical path in the constraint graph is referred to as “joginsertion”.

Unfortunately, the shearing and jog insertion methods have been appliedin sequence and have not been applied simultaneously. As a result, theexisting algorithms cannot compact most layouts very efficiently.Shearing and jog insertion techniques in sequence can optimize thelayout, but only if a sequence of the shearing and jog insertion methodsare applied sequentially where each particular step improves theobjective. The existing compaction algorithms, however, cannot applycritical path reduction techniques of shearing and jog insertionsimultaneously and therefore optimal solutions are not available formost designs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart diagram illustrating a constraint graph-basedlayout compaction method according to an embodiment of the presentinvention;

FIG. 2 is an exemplary initial layout prior to compaction;

FIG. 3 is a constraint graph representation of the initial layout ofFIG. 2;

FIG. 4 is an orthogonal constraint graph of the initial layout of FIG.2;

FIG. 5 is a flow chart diagram illustrating a method according to anembodiment of the present invention to build a critical path subgraphbased on the constraint graph of FIG. 3;

FIG. 6 is an exemplary critical path subgraph resulting from operationof the method illustration in FIG. 5;

FIG. 7 is a flow chart diagram illustrating calculation of critical edgeweights for each jogging and shear edge of the critical path subgraph ofFIG. 6; and

FIG. 8 in an exemplary final layout after compaction.

DETAILED DESCRIPTION

The following discussion is intended to provide a detailed descriptionof at least one example or embodiment of the invention and should not betaken to be limiting of the invention itself. Rather, any number ofvariations may fall within the scope of the invention which is properlydefined in the claims following this description.

Various embodiments of apparatus and methods of layout compaction whichcombine both the techniques of shearing and jog insertion are providedherein to address a problem often encountered in graph-based layoutcompaction. Such embodiments are useful in design automation of circuitlayouts such as, for example, very large scale integration (VLSI)design. During the engineering process, a high level representation of acircuit is typically converted to the gate-level by replacing functionalblocks with more specific gate-level or component-level representations.The gate-level representation is further converted to a circuit-levelrepresentation, where each gate or component is replaced with morespecific electronic circuit elements such as transistors, resistors,capacitors, diodes, etc. The circuit level representation is thentransformed to a layout representation for mapping the elements orcomponents onto a particular integrated circuit (IC) or chip. Thecircuit layout representations are used to generate masks such aspositive or negative films or the like, which are then provided to afabrication process to manufacture the chips. A plurality of such chipsare typically laid out in array or matrix fashion onto a wafer orsemiconductor substrate during the manufacturing process.

The embodiments described herein are especially relate to the circuitlayout step of design automation and more particularly to compacting thecircuit layout to improve the end product. The circuit layoutrepresentation is converted to a constraint graph representation, whichis then imposed or optimized and then converted back to an improvedlayout representation. In the constraint graph, each circuit element isconverted to a corresponding vertex between a source vertex (e.g., aside of the circuit layout) and a sink vertex (e.g., another side of thecircuit layout) in a reference direction. Minimum spacing requirementsbetween the circuit elements are represented by edges provided betweenvertices corresponding to the circuit elements. Edges can be representedby arrows with corresponding minimum length values. In the embodimentsdescribed herein, a path typically includes a set of one or morevertices between the source and sink and the edges which couple thevertices, source and sink. Sometimes a path may be the circuit elementsand sides (and the spaces between them) corresponding to the vertices,source and sink (and edges), as determined by the relevant context. Anorthogonal constraint graph is also constructed in the shear ororthogonal direction in a similar manner.

A critical path subgraph is then constructed based upon the referenceand orthogonal constraint graphs. In particular, one or more paths arechosen as the longest paths between the source and sink vertices of thereference constraint graph. One of the longest paths can be chosen asthe critical path. Each vertex included in the one or more criticalpaths of the constraint graph is included in the critical path subgraph.To construct the critical path subgraph, each vertex in the constraintgraph is converted to an input vertex for each incoming edge (e.g., anedge coupled to the vertex on the source side of the vertex), where theincoming edge is referred to as a shear edge. If the vertex has anoutgoing edge (e.g., an edge coupled to the vertex on the sink side ofthe vertex), an output vertex is created for each outgoing edge, wherethe outgoing edge is also referred to as a shear edge. Further, an edgeis created between each input vertex and each output vertex. The edgebetween the input and output vertex is a jogging edge if thecorresponding circuit element is a flexible circuit element (e.g., awire) which can change form.

For each edge in the critical path subgraph, the orthogonal constraintgraph is used to determine if the edge can be used in an optimal cutset.If not, it's weight is assigned as “None”. If the edge can be used inthe cutset, and if it is a shear edge, it is assigned a weight equal tothe shear edge's length in the constraint graph. For jogging edges, aweight is defined as the minimum of the length between the source andthe vertex, and the length between the sink and the vertex. The cutsetis determined and the critical path is reduced based on the cutset.Thus, optimization is done in the graph domain. The procedure may berepeated until the circuit layout is substantially optimized atacceptable levels of computation.

There are several rules and other information that are used to convert acircuit layout to graph representation, such as process or spacingrules, electronic connectivity information and other user-defined rulesdepending upon the elements or objects of the layout. The layout toolhas some heuristic rules to follow to initially layout the physicalcircuit elements. Such rules include spacing or proximity rules andother rules that define limits on height, width and area of the overallchip. Height, width or area limits may be necessary for the chip ifbeing placed within a larger module with certain spacing requirementsthat must be followed. Layout compaction does not attempt to reroute theelectrical connections but instead maintains the existing routing whileminimizing the spacing between elements. Some elements are “fixed” whileothers are flexible and may be modified. A fixed object or elementshould not be modified since modification would either destroy itsfunction or otherwise modify its operation or characteristics. Aflexible element is one that can be changed without substantiallyaffecting its electrical or functional characteristics, such as by“jogging” a wire or the like. It is noted, however, that fixed andflexible elements may be moved in either or both dimensions as long asspacing and other rules are maintained and not violated.

FIG. 1 is a flow chart diagram illustrating a constraint graph basedlayout compaction method according to an embodiment of the presentinvention. At a first block 101, a reference direction of a layout isselected. The reference direction may be arbitrarily chosen or mayotherwise be the more critical dimension for particular designsdepending upon height, width or area criterion. An exemplary initiallayout 200 is shown in FIG. 2. In this initial layout 200, variouscomponents, individually labeled A, B, C, D and E, are shown at variousplacements according to heuristic techniques previously described. TheA, C, D and E elements are fixed and the B element is flexible. A firstdirection is referred to as the X direction (shown in the horizontaldirection) and a second direction is referred to as the Y direction(shown in the vertical direction). A scale is shown along the Ydirection referring to units of length, such as microns. One of thedirections, such as the Y direction, will be selected as a referencedirection for optimization while the other direction, such as the Xdirection, is the shear or orthogonal direction. The reference andorthogonal directions may be swapped or exchanged during the compactionmethod (such as the orthogonal direction becoming the referencedirection and vice-versa). As shown in FIG. 2, elements C, E and D aredistributed along the X direction at the lowest Y direction value.Element B is positioned above the C, E and D elements at a particularseparation, which in this case 5 microns. Element A is placed above theB element at an offset of 5 microns and offset toward the right sideedge. It is desired to compact this initial layout 200 to improve designand operation characteristics. However, this particular initial layout200 may not be optimized by using prior art 1.5 dimensional compactiontechniques because the shearing and jog insertion approaches are doneseparately.

At first block 101, a reference direction is selected which could eitherbe the X or Y direction of the initial layout 200. In the embodimentshown; the Y direction is first chosen as the reference direction.Operation proceeds to next block 103, in which one-dimensionalcompaction techniques are performed in each direction on the initiallayout 200. In particular, the one-dimensional compaction technique isapplied to the reference direction (or the Y direction) first followedby another one-dimensional compaction applied to the X direction. It isnoted that the initial layout 200 may already be compacted such thatone-dimensional techniques may not provide further compaction. However,for many initial layouts, the one-dimensional compaction may improvecompaction somewhat before application of the methods set forth herein.

At next block 105, a critical path subgraph 600 FIG. 6) is constructed.Before the critical path subgraph 600 can be constructed, it is firstnecessary to construct a constraint graph 300 (FIG. 3) and an orthogonalconstraint graph 400 (FIG. 4) of the initial layout 200. FIG. 3 is theconstraint graph 300 of the initial layout 200 using the Y direction asthe reference direction. The elements A, B, C, D and E are ea convertedto vertices between a source vertex 301 and a sink vertex 303. Betweenany vertices including the source vertex 301 and the sink vertex 303,edges are represented by arrows having a numeric length value assignedto each edge arrow representing minimum spacing requirements between thecorresponding circuit elements. Each numeric length value represents acenter-to-center minimum spacing or distance between elements, tailinginto account dimensional size or width of the respective elements. Theminimum length values may be zero for elements that can touch or thatmust touch and cannot be separated. The minimum length values may alsoindicate direction such as having positive or negative values. As shownin FIG. 3, the vertices C, D and E can be directly touching the sourcevertex 301. A minimum length value of 15 is provided between vertices Cand B, D and B, and D and A, respectively. A length value of 11 isprovided between vertices E and D, a length value of 13 is providedbetween vertices B and A, and a length value of 10 is provided betweenelement A and the sink vertex 303.

FIG. 4 is the orthogonal constraint graph 400 of the initial layout 200.In this case, the orthogonal direction is the X direction. Each of theelements A, B, C, D and E is again converted into corresponding verticesbetween a source vertex 401 and a sink vertex 403 in the X direction,where the source and sink vertices 401, 403 represent the left and rightboundaries of the initial layout 200. Again, minimum length values areprovided between respective vertices as necessary. For example, aminimum spacing of zero is provided between the source vertex 401 andthe A vertex as well as between the A vertex and the sink vertex 403.Likewise, a minimum length value of zero is provided between the sourcevertex 401 and the B vertex, between the source vertex 401 and the Cvertex, and between the D vertex and the sink vertex 403. A minimumlength value of 20 is provided between the B vertex and the sink vertex403. A minimum length value of 10 is shown between the C and E and the Eand D vertices, respectively. As described further below, the orthogonalconstraint graph 400 is utilized to select the edges for the “cutset” toreduce a “critical path”. Initially, the minimum length values indicatethe amount that a corresponding element may be moved in the orthogonaldirection for a shear operation. The orthogonal spacing values indicatethe minimum and maximum locations in the orthogonal direction that anelement may move as well as the slack or amount of movementtherebetween. For example, the A element has a greater level of slackthan the B element, which is somewhat constrained by a minimum spacingrequirement between the two edges of the layout as well as itsrelatively large size. Although the size of some elements may bechanged, for the most part the size of the elements is fixed.

FIG. 5 is a flow chart diagram illustrating a method to construct thecritical path subgraph 600 based on the constraint graph 300 and theorthogonal constraint graph 400 of the initial layout 200. FIG. 6 is agraph of the critical path subgraph 600 resulting from the operation ofFIG. 5. At a first block 501, a list of nodes belonging to a criticalpath of the constraint graph 300 are created. With reference to FIG. 3,the critical path or paths are chosen as the longest paths between thesource and sink vertices 301, 303. Each path is referred to by theintermediate vertices and the corresponding total length, which is thesum of length values along the respective paths. For example, a firstpath EBA between the source and sink vertices 301, 303 has a length of11 plus 13 plus 10 which is 34. A second path CBA has a length of 38. Athird path DBA also has a length of 38. A final path DA has a length of25. The paths CBA and DBA are both critical paths, each having thelargest length of 38. Therefore, the vertices A, B, C and D are includedin construction of the critical path subgraph 600 as shown in FIG. 6. Atnext block 503, a next vertex referred to as NEXT_VERTEX (the firstvertex in the first iteration) from the list of vertices is selected,where each vertex will be considered one at a time. In the firstiteration, vertex C is selected as the first vertex. The vertices willbe considered in the order CDBA. At next block 505, it is queriedwhether the NEXT_VERTEX or vertex C in the first iteration, has anincoming edge. Since vertex C has an incoming edge from the sourcevertex 301, operation proceeds to block 507 in which an input vertex,referred to as I_VERTEX, is created for each incoming edge. As shown inFIG. 6, a vertex labeled I_VERTEXC is created. Also at block 507, thecorresponding incoming edge is assigned to the appropriate input vertexas a “shear” edge. As shown in FIG. 6, the incoming edge is labeled “S5”and assigned as an incoming edge to the I_VERTEXC.

Operation proceeds to next block 509 in which it is queried whether theNEXT_VERTEX has an outgoing edge. Since vertex C has an outgoing edge,operation proceeds to next block 511 in which an output vertex(O_VERTEX) is created for each outgoing edge. As shown in FIG. 6, anoutput vertex labeled O_VERTEXC is created. Also in block 511, thecorresponding outgoing edge, labeled S3, is assigned to the appropriateoutput vertex as a shear edge. As shown in FIG. 6, the S3 edge isassigned to the output vertex C and shown as leaving the output vertex Cpointing toward the B vertex. At next block 513, a “jogging” edge iscreated from each input vertex to all output vertexes for theNEXT_VERTEX. As shown in FIG. 6, a jogging edge, denoted J4, is createdfrom the input I_VERTEXC to the output O_VERTEXC. Operation thenproceeds to next block 515, where it is determined whether there are anymore vertices to consider. If so, operation returns to block 503 toconsider the next vertex from the entire list of vertices.

As shown in FIG. 6, an input vertex I_VERTEXD and an output vertexO_VERTEXD are created for vertex D, where an incoming edge S6 from thesource vertex 301 is assigned to the I_VERTEXD and the outgoing edge S4is assigned to the vertex O_VERTEXD. Also, a jogging edge, denoted J5,is created from the vertex I_VERTEXD to the vertex O_VERTEXD. The Bvertex has two incoming edges and one outgoing edge with reference tothe constraint graph 300. Therefore, two vertices, I_VERTEXB1 andI_VERTEXB2, are created along with an output vertex O_VERTEXB. The edgeS3 is assigned as an incoming edge for the vertex I_VERTEXB1 and theedge S4 is assigned as an incoming edge to the vertex I_VERTEXB2. Also,a first jogging edge, denoted J2, is created from the vertex I_VERTEXB1to the vertex O_VERTEXB. The corresponding outgoing edge, labeled S2, isassigned to the vertex O_VERTEXB. Likewise, another jogging edge,denoted J3, is created from the vertex I_VERTEXB2 to the vertexO_VERTEXB. Finally, for the vertex A, an input vertex I_VERTEXA andoutput vertex O_VERTEXA are created as shown in FIG. 6. The edge S2 isassigned as an input edge to the vertex I_VERTEXA and the correspondingoutgoing edge, labeled S1, is assigned as an output edge for the vertexO_VERTEXA. Finally, a jogging edge, denoted J1, is created from thevertex I_VERTEXA to the vertex O_VERTEXA. The edge S1 is an input edgeto the sink vertex 303. After all of the critical path vertices CDBAhave been considered, the critical path subgraph 600 is completed andoperation terminates.

Referring back to FIG. 1, after the critical path subgraph 600 iscompleted at block 105, operation proceeds to next block 107 in whichcritical edge weights are computed. FIG. 7 is a flow chart diagramillustrating calculation of the critical edge weights for each of thejogging and shear edges of the critical path subgraph 600 in accordancewith an embodiment of the invention. As first block 701, a list of thejogging and shear edges belonging to the critical path subgraph 600 isgenerated (LIST_OF_EDGES). At next block 703, a first or next edge(NEXT_EDGE) from the list of edges is considered, where each edge willbe considered one at a time. At next block 705, it is queried whetherthe edge may be used in a cutset. It is known that an edge that does nothave a weight or that has weight of “NONE” cannot be used in the cutset.It is also known that a shear edge connected to the sink or sourcevertices cannot be used in the cutset. Therefore, edges S1, S5 and S6will not be used in the cutset. Edges S2 and S3 cannot be used becauseof insufficient slack based at least in part on the orthogonalconstraint graph 400. The geometries for elements B and C cannot beeffectively moved in a horizontal direction. Analogously, if vertices ofthe constraint graph 300 cannot be split, the appropriate jogging edgesof the corresponding critical path subgraph also may not be used in thecutset. Thus, the jogging edges J1, J3, J4 and J5 cannot be used in thecutset and are given a weight of “NONE.” The appropriate values areincluded in the following table 1 of edge weights of the critical pathsubgraph 600:

TABLE 1 EDGE WEIGHTS OF THE CRITICAL PATH SUBGRAPH 600 EDGES S1 S2 S3 S4S5 S6 J1 J2 J3 J4 J5 WEIGHTS NONE NONE NONE 15 NONE NONE NONE 15 NONENONE NONE

Referring back to FIG. 7, if the edge cannot be used in the cutset,operation proceeds to next block 706 in which the weight is assigned as“NONE” and operation proceeds to block 717 described further below.Alternatively, if the edge can be used in the outset, operation proceedsto next block 707 in which it is queried whether the next edge is shear.If so, the shear edge's weight is determined as the corresponding lengthfor the shear edge from the constraint graph 300 of the initial layout200. For example, the weight of edge S4 is assigned as the length of theedge between vertices D and B, or 15. Operation then proceeds from block709 to block 717. If, however, the edge is not shear, so that the edgeis a jogging edge, operation proceeds to block 711 in which a criticalpath length to the source vertex 301, referred to as L1, is determined.At next block 713, a critical path length to the sink vertex 303,referred to as L2, is determined. Again, the L1 and L2 values are basedon the length values from the constraint graph 300. At next box 715, theweight assigned to the jogging edge is determined as the minimum of theL1 and L2 lengths. For example, the jogging edge J2 may be used in thecutset. With reference to FIG. 3, the critical path length to the sourcevertex 301 is equal to the path between the source vertex 301 and the Bvertex having a total length of 0+15=15. The critical path length to thesink vertex 303 is the length of path between the B vertex and the sinkvertex 303 which is 13+10=23. At block 715, the weight assigned to thejogging edge J2 is the minimum of (15, 23) which equals 15. The weightis shown in parentheses in FIG. 6 adjacent the J2 jogging edge. Theweight of the S4 shearing edge is shown in parenthesis as 15. At block717, it is determined whether all of the edges have been considered and,if not, operation proceeds back to block 703 to consider the next edge.After all edges are considered, operation is completed.

Referring back to FIG. 1, after the critical edge weights are determinedat block 107, at next block 109, an “optimal” outset is determined basedon the critical edge weights. Methods for determining a cutset are wellknown. In the present case, the set of edges that achieve asubstantially minimum or a substantially maximum cutset depending uponthe particular implementation are determined. A cutset is a set of edgesthat divide the graph into two separate groups of vertices. The desiredor optimal cutset is either the substantially minimum or thesubstantially maximum cutset based on the sum of the weights of theedges in the particular cutset. As shown in FIG. 6, since only two edgesare available for the cutset, including the J2 jogging edge and the S4shear edge, an optimal cutset 601 is defined as a unique cutset thatpasses through the edges J2 and S4 to divide the graph into two groups.At next block 111, the critical path is reduced based upon the cutsetdetermined at block 109. The critical path is reduced by effectivelyremoving the cutset edges J2 and S4 from the critical path subgraph 600.Removing a shear edge denotes moving the corresponding circuit elementby a certain amount based upon the amount of slack determined by theorthogonal constraint graph 400, otherwise referred to as “shearmovement” along the optimal cutset. Removing the S4 shear edge denotesmoving the component in the orthogonal direction to a new location asshown by the final layout 800 shown in FIG. 8. Removing a jogging edgedenotes a jog insertion by breaking the corresponding element intomultiple elements and inserting a jog. This is done for flexibleelements, such as the B element. For example, removal of the J2 joggingedge denotes breaking the B element into elements B1 and B2 as shown inFIG. 8, and inserting a jog element B3 between the B1 and B2 elements.Thus, a jog insertion has been performed along the optimal cutset. Inthis manner, the critical path of the critical path subgraph 600 hasbeen reduced, resulting in a final layout 800 that is compacted relativeto the initial layout 200.

It is understood and appreciated that the cutset clearly illustrateslayout compaction in two dimensions and further that the shearing andjog insertion methods are performed simultaneously. It is noted that,although the illustrated embodiment shows the optimal cutset asincluding a jogging edge and a shear edge, the cutset may comprise anycombination of jogging and shear edges to achieve a substantiallyminimal or substantially maximal cutset.

At next block 113, it is determined whether the critical path wasreduced at block 111. Since a cutset was found block 109 and thecritical path was reduced at block 111, operation proceeds to block 115to perform a flag operation. A flag (initially cleared) is set at block115 denoting that the critical path has been reduced in the currentiteration. Operation then returns to block 103 to repeat theone-dimensional compaction in each of the reference and orthogonaldirections. The procedure of blocks 103, 105, 107, 109, 111, 113 and 115is repeated for the selected reference as many times until the criticalpath is no longer reduced for the selected reference direction. If thecritical path is not reduced as determined at block 113, operationproceeds to block 117 at which the flag is checked to determine if thecritical path was reduced at all for the reference direction. Thisoccurs when at least two iterations of the compaction steps areperformed as indicated by the flag being set at block 115. If the flagis set, operation proceeds to block 119 in which the flag is cleared andthen operation proceeds to block 121 in which the orthogonal direction(X) is selected as the reference direction. Consequently, the oldreference direction (Y) becomes the orthogonal direction. Operation thenreturns to block 103 to repeat the compaction operations at blocks 103,105, 107, 109, 111, 113 and 115 for the orthogonal direction.

The compaction operation is repeated for the orthogonal direction in asimilar manner as the reference direction for as many times as necessaryuntil the critical path is no longer reduced as determined at block 113.If the flag has not been set as determined at block 117, then there hasbeen no reduction at all in the critical path for the selected referencedirection. Operation then proceeds to block 123 in which it isdetermined whether both dimensions have been selected and considered.This ensures that both dimensions (the X and Y directions) are eachconsidered at least once in the event that the first selected referencedirection does not result in any reduction of the critical path. If bothdimensions have not been selected as determined at block 123, operationproceeds to block 121 in which the directions are swapped in order toperform the compaction operation for both directions, and operationproceeds back to block 103. After both dimensions have been selected andconsidered at least once and when the critical path is no longerreduced, as determined at block 123, operation is completed.

It is appreciated that the an embodiment of the present inventionprovides a method of layout compaction that combines both the techniquesof shearing and jog insertion simultaneously. This provides superiorresults that achieve a better layout density as compared to othertechniques that primarily consider one direction at a time. As a result,layouts are achieved that exhibit superior electrical characteristicsdue to reduced area and reduced parasitic loads on the signal netlayouts. The present compaction technology is essential to other areasof silicon design automation such as process migration. Standard celllayouts may also be synthesized into a library in several technologies.An embodiment of the present invention also may provide better yield byproviding smaller geometries on each wafer for fabrication. The new chipmay run faster and may even consume less power.

Because the above detailed description is exemplary, when “oneembodiment” is described, it is an exemplary embodiment. Accordingly,the use of the word “one” in this context is not intended to indicatethat one and only one embodiment may have a described feature. Rather,many other embodiments may, and often do, have the described feature ofthe exemplary “one embodiment.” As used above, when the invention isdescribed in the context of one embodiment, that one embodiment is oneof many possible embodiments of the invention.

Notwithstanding the above caveat regarding the use of the words “oneembodiment” in the detailed description, it will be understood by thosewithin the art that if a specific number of an introduced claim elementis intended, such an intent will be explicitly recited in the claim, andin the absence of such recitation no such limitation is present orintended. For example, in the claims below, when a claim element isdescribed as having “one” feature, it is intended that that element belimited to one and only one of the feature described. Furthermore, whena claim element is described in the claims below as including orcomprising “a” feature, it is not intended that the element be limitedto one and only one of the feature described. Rather, for example, theclaim including “a” feature reads upon an apparatus or method includingone or more of the feature in question. That is, because the apparatusor method in question includes a feature, the claim reads on theapparatus or method regardless of whether the apparatus or methodincludes another such similar feature. This use of the word “a” as anonlimiting, introductory article to a feature of a claim is adoptedherein by Applicants as being identical to the interpretation adopted bymany courts in the past, notwithstanding any anomalous or precedentialcase law to the contrary that may be found. Similarly, when a claimelement is described in the claims below as including or comprising anaforementioned feature (e.g., “the” feature), it is intended that thatelement not be limited to one and only one of the feature described.Furthermore, the use of introductory phrases such as “at least one” and“one or more” in the claims should not be construed to imply that theintroduction of another claim element by the indefinite articles “a” or“an” limits any particular claim containing such introduced claimelement to inventions containing only one such element, even when thesame claim includes the introductory phrases “one or more” or “at leastone” and indefinite articles such as “a” or “an.” The same holds truefor the use of definite articles.

The above description is intended to describe at least one embodiment ofthe invention. The above description is not intended to define the scopeof the invention. Rather, the scope of the invention is defined in theclaims below. Thus, while particular embodiments of the presentinvention have been shown and described, it will be obvious to thoseskilled in the art that, based upon the teachings herein, variousmodifications, alternative constructions, and equivalents may be usedwithout departing from the invention claimed herein. Consequently, theappended claims encompass within their scope all such changes,modifications, etc. as are within the true spirit and scope of theinvention. Furthermore, it is to be understood that the invention issolely defined by the appended claims. The above description is notintended to present an exhaustive list of embodiments of the invention.Unless expressly stated otherwise, each example presented herein is anonlimiting or nonexclusive example, whether or not the termsnonlimiting, nonexclusive or similar terms are contemporaneouslyexpressed with each example. Although an attempt has been made tooutline some exemplary embodiments and exemplary variations thereto,other embodiments and/or variations are within the scope of theinvention as defined in the claims below.

1. A method of compacting a circuit layout, the method comprising: determining a critical path of the circuit layout, the critical path having a length not less than a length of each other path of the circuit layout; representing the critical path to include a plurality of vertices and a plurality of edges, each one of the vertices being coupled to another of the vertices by an edge, the plurality of vertices including a flexible vertex corresponding to a flexible element of the circuit layout, the plurality of edges including a first shear edge; representing the flexible vertex to include a first jogging edge; and determining an optimal cutset of the graph of the critical path, the cutset including at least one of the group consisting of the first jogging edge and the first shear edge.
 2. The method of claim 1 wherein the optimal cutset includes both the first jogging edge and the first shear edge.
 3. The method of claim 1 further comprising: reducing the length of the critical path by performing a jog insertion and a shear movement along the optimal cutset.
 4. The method of claim 1 further comprising: reducing the length of the critical path by performing at least one of the group consisting of a jog insertion at the first jogging edge of the flexible vertex and a shear movement at the first shear edge.
 5. The method of claim 1 further comprising: reducing the length of the critical path by performing a jog insertion at the first jogging edge of the flexible vertex and a shear movement at the first shear edge.
 6. The method of claim 1 further comprising: performing a one-dimensional compaction of the circuit layout in a first direction before determining the critical path; and performing a one-dimensional compaction of the circuit layout in a second direction after performing the one-dimensional compaction in the first direction.
 7. The method of claim 6 further comprising selecting the critical path in the first direction of the circuit layout.
 8. The method of claim 1 wherein: each vertex corresponds to a circuit element of the circuit layout; and each edge defines a minimum space relationship between circuit elements corresponding to vertices to which each edge is coupled.
 9. The method of claim 1 wherein the flexible vertex is represented to further include a second jogging edge; the optimal cutset is determined to include at least one of the first and second jogging edges and to include the shear edge.
 10. The method of claim 9 wherein the plurality of edges further includes a second shear edge; and the optimal cutset is determined to include at least one of the first and second jogging edges and at least one of the first and second shear edges.
 11. A computer program product encoded in computer readable media, the computer program product comprising: first instructions, executable on a data processing system, for determining a critical path of a circuit layout; second instructions, executable on the data processing system, for representing the critical path to include a plurality of vertices and a plurality of edges, each one of the plurality of vertices being coupled to another of the vertices by an edge, the plurality of vertices including a flexible vertex corresponding to a flexible element of the circuit layout, the plurality of edges including a first shear edge; third instructions, executable on the data processing system, for representing the flexible vertex to include a first jogging edge; and fourth instructions, executable on the data processing system, for determining a optimal cutset of the graph of the critical path, the cutset including at least one of the group consisting of the first jogging edge and the first shear edge. 